Magnetic memory such as magnetic random access memory (MRAM) is a non-volatile, semiconductor-based memory technology in which magnetic, rather than electrical, charges are used to store bits of data.
Typically, magnetic memory devices comprise a plurality of memory cells or bits that are arranged in a two-dimensional array. Each memory cell is configured to store a single bit of information, i.e., a logic value “1” or a logic value “0.” Each memory cell of the array is coupled to a column conductor and a row conductor at a cross-point of the conductors.
To write data to a target memory cell, current flow is provided through the column conductor and row conductor associated with the target memory cell. The magnetic fields created by the flow of electrons through the conductors induce magnetic fields to set a permanent magnetization in a sense layer of the memory cell to control its resistivity and, therefore, control the state of the cell.
Reading of a target memory cell can be accomplished in various ways. In one method, an “equipotential” reading scheme is used. This reading scheme is represented in FIG. 1. In this figure, a cross-point array 100 is illustrated that includes a plurality of memory cells 102 that are represented by resistors. Each of the memory cells 102 is electrically coupled to a column conductor 104 and a row conductor 106. During an equipotential read, each column conductor 104 is connected to an array voltage, VA, except for a column conductor that is coupled to a target memory cell, T. Similarly, each row conductor 106 except the row conductor coupled to the target memory cell, T, is connected to VA.
As indicated in FIG. 1, the column conductor 104 coupled to the target memory cell, T, is connected to a sense voltage, VA′, which approximates VA and which, as is discussed below, is used to sense the memory state of the target memory cell. As is also shown in FIG. 1, the row conductor 106 coupled to the target memory cell, T, is connected to ground. With this arrangement, array current, IA, will flow through the non-target memory cells 102 coupled to the row conductor 106 that is also coupled to the target memory cell, T. In addition, sense current, Isense, flows through the target memory cell, T. Due to the application of VA to the row conductors not coupled to the target memory cell, T, sneak currents are minimized.
FIG. 2 illustrates an example sensing circuit 200 presently used to determine the memory state of target memory cells. As indicated in this figure, the sensing circuit 200 includes an operational amplifier 202, a first field-effect transistor (FET) 204, a second FET 206, a capacitor 208, a comparator 210, and a counter/memory 212. The operational amplifier 202 receives an input of VA into its positive terminal and outputs VA′ to the column conductor coupled to the target memory cell. The circuit 200 is further connected to a voltage source, Vdd, whose current flow is controlled with the FET 206 via a control line 214. By way of example, the FET 206 comprises a p-type metal-oxide semiconductor field-effect transistor (MOSFET).
During a read operation, VA is applied to the array in the manner described above with regard to FIG. 1. In addition, Vdd is applied to generate the sense current, Isense, which passes through the FET 204, e.g., an n-type MOSFET, to flow to the target memory cell. Current also flows to the capacitor 208 so as to increase the potential of the capacitor until it is equal to Vdd. The operational amplifier 202 adjusts the gate of the FET 204 to ensure that VA′ is substantially equal to VA. Once a steady-state condition is obtained, the amplifier 202 opens the gate of the FET 206 such that the capacitor 208 provides the current needed to maintain VA′.
The capacitor 208 slowly discharges its voltage until its voltage is reduced to a reference voltage, Vref, that, along with the capacitor voltage, is input into the comparator 210. This discharge is depicted in FIG. 3, which illustrates capacitor voltage, Vcap, over time. As indicated in the figure, the voltage of the capacitor increases to Vdd and is then depleted until reaching, and dropping below, Vref. The time required to reach Vref depends upon the resistance of the target memory cell and, therefore, provides an indication of the memory state of the cell. For instance, in a scheme in which a higher resistance indicates a logic value “1” and a lower resistance indicates a logic value “0,” a logic value “0” is indicated if Vref is reached after the elapse of time, t1, and a logic value “1” is indicated if Vref is reached after the elapse of time, t2. The time it takes for the voltage of the capacitor 208 to drop to Vref is measured and stored by the counter/memory 212.
FIG. 4 depicts the voltage applied to the array during a read. As indicated in this figure, VA must be applied to the array at least until the time required for the capacitor voltage to be reduced to Vref. Although this amount of time is not large in an absolute sense, for instance on the order of 5 to 15 microseconds (μs), in that VA is applied to each memory cell coupled to the target memory cell's row conductor, a relatively large amount of current is burned in the array while waiting for the capacitor to discharge its voltage. In the aggregate, the amount of current spent during reading becomes significant.
Another known reading method uses a “non-equipotential” reading scheme. This reading scheme is represented in FIG. 5. As shown in this figure, VA is applied only to the row conductor 106 that is coupled to the target memory cell, T; all other row conductors 106 are tied to ground. The column conductor 104 coupled to the target memory cell, T, is connected to a sense circuit 600 that is illustrated in FIG. 6. The sense circuit 600 includes an analog-to-digital (A/D) converter 602 and a memory 604. In this figure, the resistance provided by the column conductor can be represented by a voltage divider 606 that comprises a resistor RT, representing the resistance of the target memory cell, and resistors R1 and R3, representing the parallel combination of the resistances of all the other memory cells coupled to the target memory cell's column conductor (only three shown in FIG. 5).
During a read operation, the A/D converter 602 receives a voltage input equal to the voltage on the column conductor that is coupled to the target memory cell. This voltage is then converted into a digital value and compared multiple times to reference values to determine the resistance of the target memory cell. The conversion and comparison process normally requires a relatively long amount of time where extremely accurate measurement is required, for instance, approximately 50 to 100 μs. FIG. 7 illustrates the time required to make the state determination. In particular, FIG. 7 shows the A/D converter output being invalid for an extended period of time until finally becoming valid at tvalid. Until valid data is obtained, VA must be applied to the array. This application of voltage is depicted in FIG. 8 which shows VA being applied at least until time tvalid. Accordingly, as in the equipotential reading scheme, a relatively large amount of current is used to obtain the data stored by the target memory cell. Again, the amount of current lost can be significant when taken in the aggregate.